A state machine, also referred to as a finite automaton, represents a model of a system composed of states, state transitions, and actions. The automaton is referred to as “finite” when the quantity of states which the automaton is able to accept is finite.
A state stores the information concerning the past; i.e., the state reflects the changes in the input since the start of the system up to the present point in time. A state transition indicates a change in the state of the automaton, and is described by a logical condition that must be met in order to allow the state transition. An action is the output of the automaton which occurs in a certain situation.
A state machine may be represented as a state transition diagram. In addition, different types of transition tables may be utilized.
State machines are primarily used in the development of digital circuits and in the modeling of the application characteristics of control systems, for hardware and software as well as for mixed systems.
A number of methods are known for testing electronic units or electronic hardware. The aim of these methods is to recognize faults in the hardware and to eliminate then, which is also referred to as “debugging.”
The so-called Joint Test Action Group (JTAG) refers to a standard which describes a collection of methods for testing and debugging electronic hardware directly in the circuit. The so-called boundary scan test is one method that is presently widely used.
The method is used to test the functionality of integrated circuits while they are in their working environment. For this purpose, these integrated circuits may be soldered to a printed circuit board, for example. A JTAG-capable IC may have components which are completely separate during normal operation and which thus do not impair the function of the component. Only by activating the JTAG function by a sequence is the control of certain functions transferred to JTAG. The JTAG interface to the outside environment is generally implemented as a shift register.
A JTAG component is composed essentially of the following parts:
the test access port (TAP) together with control lines, which is also referred to as a JTAG port or a JTAG interface;
the TAP controller, which controls a state machine which controls the test logic; and
two shift registers, the instruction register (IR) and the data register (DR).
The test access port (TAP) includes five control lines:    1. test data input (TDI): serial input of the shift register;    2. test data out (TDO): serial output of the shift register;    3. test clock (TCK): the clock signal for the entire test logic system;    4. test mode select input (TMS): this line determines into which subsequent state the state machine of the test access port skips upon the next positive signal edge of the TCK signal; and    5. test reset (reset of the test logic system): this signal is optional.
Multiple integrated circuits may be connected to a JTAG interface. This results in a series connection of the shift registers of the affected ICs.
The TAP controller is a state automaton which is clocked by the TCK and controlled by the TMS line. The TMS line determines into which subsequent state a skip is made during the next clock pulse. The TAP controller has six stable states, i.e., states in which the system may remain for multiple clock pulses.
JTAG thus provides an at least partially standardized interface. A microcontroller may be accessed via this interface without assistance from the microcontroller.
Various methods and languages are known for accessing the microcontroller via the standardized interface, the TAP with the aid of the TAP controller, which may be described as a state machine. Such a language or file format is the so-called Serial Vector Format (SVF), for example.
SVF is a file format for exchanging boundary scan test vectors. SVF was developed with the aim of describing JTAG operations regardless of the manufacture.
SVF files contain a sequence of SVF instructions which describe how the JTAG state machine is to be run through. The two essential commands are the scan instruction register (SIR) and the scan data register (SDR) shift instructions. SIR carries out a shift operation into the instruction register, and SDR carries out a shift operation into the data register that is active at that moment, in each case with an indicated number of bits.
SVF is an ASCII format that is easily read and modified.
A disadvantage of SVF is that the states of the state machine of the TAP controller may run through only in a predetermined manner. If this is not sufficient, it is not possible to use SVF.